JTS15

The JTS15S core is a unique method of reducing the flash programming time vie the IEEE1149.1 interface. This is achieved by the minimizing the size of the boundary scan register or "BSR" which is connected to the flash device.

This method of decreasing the flash programming time enables smooth integration with the ATPG tool vendors (Asset-Intertech, Goepel Electronic, Jtag Technologies) as Firecron provides the BSDL file for the JTS15S IP core which is then imported directly into the ATPG vendor tool suites, along with the PCB netlist information and the image to be programmed into the flash device.

By performing IEEE1149.1 chain partitioning using a Firecron Gateway device it is possible to implement the JTS15S device on a PCB without the impact of user intervention on the manufacturing line. The result is clear:

Reduces flash programming times by 6X
User free interaction on production line when used in conjunction with a Firecron Gateway (JTS03 or JTS06 device)
Ability to place safe states on the PCB, where the JTS15S core is loaded, which negates the loss of control of the boundary scan register in that device
JTS15S IEEE1149.1 TAP port operates at high speed reducing flash programming times. By using JTS03 or JTS06 devices with slow TAP TCK rates can be switched out of the chain during flash programming

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JTS15 Core