Clock I.P.

The Clock I.P Core (IP-102) provides a method of using boundary scan to detect and measure the period of signal transitions on a PCB, primarily targeted at clock but can alos be used to detect data patern as well as signal transitions. The solution involves programming the IP-102 core into a programmable logic device where the signal to be tested is are connected.

 

Firecron generates the  SVF test for the IP-102 which is then executed on the IP-102 and  provides the actual measurement of the required signal. The SVF test can be executed in two ways, either via an SVF player or utilizing the ATPG vendors CPLD programming software and the BSDL file for the IP-102.

 

If the user wishes to use the SVF file generated for the IP-102 device via a gateway device then the Firecron svf2bvf windows executable will  then add the required gateway knowledge to the SVF file and exports this SVF file which can then be played.

 

The tolerance of the result is defined by the accuracy of the TCK clock rate being used for the test.