JTS family

The JTS family of gateway devices are the premier range of gateway devices, these devices form the cornerstone of any D.F.T test strategy. The Gateway allows the designer the freedom to implement a comprehensive and well implemented design stratagy with only one access point for everything from interconnect testing to Processor debugging. The devices themselves range form 3 to 15 LSP's or daughter chains, which under software control can be oriented in any permutation required for that test. The key is that all the devices are based on the IEEE1149.1 standard and are fully supported within all the ATPG vendors tool sets.

The Firecron solution is based on and supports the industry standard IEEE1149.1 format

Device Features include:

All the Devices are Multi-Drop Addressable via the IEEE 1149.1 protocol
Up to 59 individual Multi- Drop addresses
Support for 3 and 6 local scan chains addressable via the IEEE 1149.1 interface
Ability to Tri State the Local scan port signals to enable another test tool to gain access
Support for Pass-through mode of operation enabling the user to bypass the device
Support for Once Enable mode for MPC series processors debug tool, through the JTS03/6 devices
Support for the IEEE 1149.1 USERCODE instruction, where the data can be programmed on the I/O of the device
Support for Status instruction enabling non-intrusive monitoring of the system card
Local Scan port enable signal provides the ability to use non IEEE 1149.1 compliant devices that require JTAG enable signal
Provides the ability to initiate Self Test on a remote PCB via a standard IEEE 1149.1 command.

For more information please open pdf files below.

JTS10 Low resolution file